Publications - Zdeněk Pohl
Journal articles (5)
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1. * Zdeněk Pohl, Milan Tichý, Jiří Kadlec: Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA. EURASIP Journal on Advances in Signal Processing 2008 (2008), 1-11. Download |
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2. * J. N. Coleman, C. I. Softley, Jiří Kadlec, R. Matoušek, Milan Tichý, Zdeněk Pohl, Antonín Heřmánek, N. F. Benschop: The European Logarithmic Microprocessor. IEEE Transactions on Computers 57:4 (2008), 532-546. Download |
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3. * Martin Daněk, Petr Honzík, Jiří Kadlec, Zdeněk Pohl, Rudolf Matoušek: Platforma s částečnou dynamickou rekonfigurací FPGA. Automa 12:5 (2006), 40-43. |
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4. * Rudolf Matoušek, Martin Daněk, Zdeněk Pohl, Roman Bartosinski, Petr Honzík: Reconfigurable System-on-a-Chip. Syndicated 5:2 (2005), 1-3. |
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5. * Martin Daněk, Petr Honzík, Jiří Kadlec, Rudolf Matoušek, Zdeněk Pohl: Reconfigurable system on programmable chip platform. ATMEL Applications Journal, 9-12. |
Conference papers (24)
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1. * H. Isakovic, R. Grosu, D. Ratasich, Jiří Kadlec, Zdeněk Pohl, S. Kerrison: A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC2. Computer Safety, Reliability, and Security : SAFECOMP 2017 Workshops, ASSURE, DECSoS, SASSUR, TELERISE, and TIPS, 127-140. Springer, Cham 2017. Download |
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2. * M. W. Van Tol, Zdeněk Pohl, Milan Tichý: A Framework for Self-adaptive Collaborative Computing on Reconfigurable Platforms. Advances in Parallel Computing, 579-586. IOS Press BV, Amsterdam 2012. Download |
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3. * Zdeněk Pohl, Milan Tichý: Resource Management for the Heterogeneous Arrays of Hardware Accelerators. Proceedings of 21st International Conference on Field Programmable Logic and Applications, 486-489. IEEE, Chania 2011. Download |
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4. * Zdeněk Pohl, Milan Tichý: RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator. Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL), 774-777. IEEE, Delft 2007. |
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5. * Martin Daněk, Antonín Heřmánek, Petr Honzík, Jiří Kadlec, Rudolf Matoušek, Zdeněk Pohl: GIN - notetaker for blind people: An example of using dynamic reconfiguration of FPGAs. ACACES 2005. Advanced Computer Architecture and Compilation for Embedded Systems, 15-18. HiPEAC Network of Excellence, Ghent 2005. |
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6. * Zdeněk Pohl, Jiří Kadlec, P. Šůcha, Z. Hanzálek: Performance tuning of interative algorithms in signal processing. Proseedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005, 699-702. Academy of Finland, Tampere 2005. |
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7. * Martin Daněk, Zdeněk Pohl, K. Nasi, T. Karoubalis: Figaro - an automatic tool flow for designs with dynamic reconfiguration. Proceedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005, 590-593. Academy of Finland, Tampere 2005. |
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8. * P. Šůcha, Zdeněk Pohl, Zdeněk Hanzálek: Scheduling of iterative algorithms on FPGA with pipelined arithmetic unit. Real-Time and Embedded Technology and Applications Symposium, 404-412. IEEE Computer Society, Washington DC 2004. Download |
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9. * Martin Daněk, Petr Honzík, Jiří Kadlec, Rudolf Matoušek, Zdeněk Pohl: Reconfigurable system-on-a-programmable-chip platform. Proceedings of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 21-28. Institute of Informatics SAS, Bratislava 2004. |
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10. * Zdeněk Pohl, Jan Schier, Miroslav Líčko, Antonín Heřmánek, Milan Tichý: Logarithmic arithmetic for real data types and support for Matlab/Simulink based rapid-FPGA-prototyping. Proceedings of the International Parallel and Distributed Processing Symposium. IPDPS 2003, 1-6. IEEE Computer Society Press, Los Alamitos 2003. |
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11. * Zdeněk Pohl: Logarithmic number system and floating-point arithmetics an FPGA. Počítačové Architektury & Diagnostika PAD 2003, 9-16. VUT, Brno 2003. |
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12. * Rudolf Matoušek, Zdeněk Pohl, Martin Daněk, Jiří Kadlec: Dynamic reconfiguration of Atmel FPGAs. UK ACM SIGDA 3rd Workshop on Electronic Design Automation, 1-4. University of Southampton, Southampton 2003. |
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13. * Rudolf Matoušek, Zdeněk Pohl, Martin Daněk, Jiří Kadlec: Dynamic reconfiguration of FPGAs. Recent Trends in Multimedia Information Processing. Proceedings, 288-291. Czech Technical University, Prague 2003. |
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14. * Antonín Heřmánek, Zdeněk Pohl, Jiří Kadlec: FPGA implementation of the adaptive lattice filter. Lecture Notes in Computer Science. 2778. Field-Programmable Logic and Applications. Proceedings of the 13th International Conference, 1095-1098. Springer, Berlin 2003. |
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15. * Rudolf Matoušek, Martin Daněk, Zdeněk Pohl, Jiří Kadlec: Dynamic runtime partial reconfiguration in FPGA. ECMS 2003. 6th International Workshop on Electronics, Control, Measurement and Signals, 294-298. Technical University, Liberec 2003. |
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16. * Zdeněk Pohl, Rudolf Matoušek, Jiří Kadlec, Milan Tichý, M. Líčko: Lattice adaptive filter implementation for FPGA. FPGA 2003 ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, 246. ACM, Monterey 2003. |
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17. * Zdeněk Pohl, M. Líčko: Utilization of the HSLA toolbox for the FPGA prototyping. MATLAB 2002. Sborník příspěvků 10. ročníku konference, 462-468. VŠCHT, Praha 2002. |
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18. * Rudolf Matoušek, Milan Tichý, Zdeněk Pohl, Jiří Kadlec, C. Softley: Logarithmic number system and floating-point arithmetics on FPGA. Lecture Notes in Computer Science. 2438. Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, 627-636. Springer, Berlin 2002. |
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19. * Miroslav Líčko, Milan Tichý, Antonín Heřmánek, Rudolf Matoušek, Zdeněk Pohl: Prototyping of DSP algorithms on FPGA. POSTER 2002, 2. FEL ČVUT, Praha 2002. |
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20. * Jiří Kadlec, Milan Tichý, Antonín Heřmánek, Z. Pohl, M. Líčko: Matlab Toolbox for high-level bit-exact emulation of HandelC VHDL FPGA designs. Design, Automation and Test in Europe DATE˙02, 264. IEEE, Los Alamitos 2002. |
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21. * R. Matoušek, Z. Pohl, Jiří Kadlec, Milan Tichý, Antonín Heřmánek: Logarithmic arithmetic core based RLS LATTICE implementation. Design, Automation and Test in Europe DATE 02, 271. IEEE, Los Alamitos 2002. |
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22. * Miroslav Líčko, Rudolf Matoušek, Zdeněk Pohl: Utilization of Matlab for the logarithmic processor development. Sborník příspěvků 9.ročníku konference MATLAB 2001, 222-225. VŠCHT, Praha 2001. |
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23. * Miroslav Líčko, Zdeněk Pohl, Rudolf Matoušek, Antonín Heřmánek: Tuning and implementation of DSP algorithms on FPGA. Sborník příspěvků 9.ročníku konference MATLAB 2001, 226-230. VŠCHT, Praha 2001. |
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24. * Antonín Heřmánek, Jiří Kadlec, Rudolf Matoušek, Miroslav Líčko, Zdeněk Pohl: Pipelined logarithmic 32bit ALU for Celoxica DK1. Sborník příspěvků 9.ročníku konference MATLAB 2001, 72-80. VŠCHT, Praha 2001. |
Other publications (13)
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4. * Zdeněk Pohl: Výstup z Celoxica DK jako BlackBox komponenta Systém Generátoru. ÚTIA AV ČR, Praha 2007. |
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7. * K. Nasi, Martin Daněk, T. Karoubalis, Zdeněk Pohl: Figaro: An automatic tool flow for designs with dynamic reconfiguration. Abstract. FPGA 2005 - ACM/SIGDA Thirteenth ACM International Symposium on Field-Programmable Gate Arrays, 262. ACM, Monterey 2005. |
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10. * Zdeněk Pohl, Jiří Kadlec, Miroslav Líčko, Rudolf Matoušek, Milan Tichý: Lattice IP Core used in Real-time Lattice Demo on XESS Board. (Program). ÚTIA AV ČR, Praha 2003. |
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11. * Zdeněk Pohl, Jiří Kadlec, Milan Tichý: RLS Lattice - Celoxica RC200 Demo. (Program). ÚTIA AV ČR, Praha 2003. |
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12. * Miroslav Líčko, Jan Schier, Zdeněk Pohl, Jiří Kadlec, Milan Tichý, Rudolf Matoušek, Antonín Heřmánek: Logarithmic Arithmetic for Real Data Types and Support for MATLAB/SIMULINK Based Rapid-FPGA-Prototyping. Research Report 2069. ÚTIA AV ČR, Praha 2002. |
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13. * J. N. Coleman, Jiří Kadlec, Rudolf Matoušek, Zdeněk Pohl, Antonín Heřmánek: The European Logarithmic Microprocessor - a QRD RLS Applications. Research Report 2038. ÚTIA AV ČR, Praha 2001. |