Publication details

Conference Paper (international conference)

FPGA implementation of logarithmic unit core

Kadlec Jiří, Matoušek Rudolf, Líčko Miroslav

: Embedded Intelligence 2001, p. 547-554

: Design & Elektronik, (Nürnberg 2001)

: Embedded Intelligence 2001, (Nürnberg, DE, 14.02.2001-16.02.2001)

: AV0Z1075907

: HSLA 33544, ESPRIT, 212 HSLA, Commission EC

: field programmable gate array

(eng): Implementation of floatig point in FPGA (Field Programmable Gate Arrays) is not easy. Paper presents FPGA core which implements these operations by representation of floating point numbers as 32-bit integer (fixed point) logarithm. Basic arithmetical operations are performed in the logarithm numbering system (LNS) suitable for FPGA. First, we describe Matlab library emulating bit-exactly the properties of the final hardware.

: 09G, 09J

: JC